1. Field of the Invention
The present invention relates to a device for interfacing asynchronous data, and more particularly, to a device for interfacing asynchronous data using a first-in-first-out (FIFO) for preventing cutoff in data transfer by transferring the asynchronous data in accordance with a data transfer information signal while best satisfying a transfer request from a host between two devices that transfer bi-directional asynchronous data. The present application is based on Korean Patent Application No. 2002-8306, filed Feb. 16, 2002, which is incorporated herein by reference.
2. Description of the Related Art
In a digital communication or storage system, hosts may have different data processing rates for processing a communication channel or disk data, for processing error correction and error detection data, for processing a compressing or decompressing signal, and for processing information. In order to construct a digital communication or storage system using processors having different data processing rates, a device is required for thoroughly transferring or storing and restoring asynchronous data.
For transferring the asynchronous data between two devices having different data processing rates, a method for buffering a data overflow caused by the difference in the data processing rates by using an FIFO is extensively used. The FIFOs are divided into an asynchronous FIFO and a synchronous FIFO. In the asynchronous FIFO, data input and output are performed without being synchronized with a clock, so that the input data is output after a predetermined delay. In the synchronous FIFO, the data is input and output in synchronization with the clock.
As shown in FIG. 1, a conventional device for interfacing asynchronous data comprises: a host computer 110, an interface unit 120, a data buffer control unit 130, and a data buffer 140. In this case, the interface unit 120 is formed of an FIFO 120-1 and an interface control unit 120-2.
Two kinds of operation mode are defined in referring to the transfer direction of the data. An operation mode in which the data is transferred from the data buffer 140 to the host computer 110 is defined as a decoding mode, and an operation mode in which the data is transferred from the host computer 110 to the data buffer 140 is defined as an encoding mode.
First, the decoding mode will be described.
When a transfer request signal DREQ is input from the host computer 110 to the interface control unit 120-2, the interface control unit 120-2 outputs a data read request signal REQ to the data buffer control unit 130. Accordingly, when the data buffer control unit 130 generates a data buffer enable signal ACK, and the interface control unit 120-2 outputs a write signal WE to the FIFO 120-1, a data signal BDATA read out from the data buffer 140 is stored in the FIFO 120-1. When the FIFO 120-1 is not empty, namely an empty signal EMPTY is not generated in the FIFO 120-1, a read signal RE is output to the FIFO 120-1. Consequently, a data signal DATA in the FIFO 120-1 and a transfer information signal DACK are output to the host computer 110. If the empty signal EMPTY is generated by not reading out the data signal BDATA from the data buffer 140, the data and transfer information signals DATA and DACK are not output. Moreover, if a full signal FULL is generated in the FIFO 120-1, the data read request signal REQ is not output until the full signal FULL is removed. The process is iterated until the transfer request signal DREQ is eliminated.
Next, the operation in the encoding mode will be described.
The transfer request signal DREQ is output to the host computer 110. In accordance with the transfer information signal DACK input from the host computer 110, the data signal DATA is input to and stored in the FIFO 120-1 by the write signal WE from the interface control unit 120-2. When the empty signal EMPTY is not generated in the FIFO 120-1, the data read request signal REQ is output to the data buffer control unit 130. If the data buffer enable signal ACK is generated from the data buffer control unit 130, the interface control unit 120-2 outputs the read signal RE to the FIFO 120-1. Accordingly, the data signal BDATA stored in the FIFO 120-1 is output to the data buffer 140 for the data buffer to store the data signal BDATA. If the empty signal EMPTY is generated in the FIFO 120-1 by not reading out the data from the host computer 110, the interface unit 120 does not output the data signal BDATA and the data read request signal REQ. Moreover, if the full signal FULL is generated in the FIFO 120-1, the transfer request signal DREQ is not output until the full signal FULL is removed. The process is iterated until all of the desired data is input.
The described conventional device for interfacing the asynchronous data has disadvantages as follows:
First, since the interface with the host is asynchronous, direct input of an interface signal from the host computer to the interface control unit causes a synchronizing problem, so that errors may occur in the interface control unit.
Second, the asynchronous data input from the host is difficult to store appropriately in the FIFO.
Third, it is difficult to synchronize the timing for storing the asynchronous data in the FIFO with the timing for inputting the interface signal to the interface control unit.